This invention is related generally to the field of analyzing simulated integrated circuits, and specifically to the field of detecting crosstalk induced functional failure in designs of electronic circuitry.
As processing technology for integrated circuits scales down to 0.13 micron and below, capacitive crosstalk is having an increasingly adverse effect on the functionality of the circuits. For example, crosstalk noise can cause circuit functional failure and noise induced delay changes (speedup or slowdown), leading to increasing number of chip failures. Traditional noise analysis approaches are unable to accurately and efficiently detect functional failures resulting from crosstalk noise.
Early research on noise analysis focused on functional failures caused by charge sharing, crosstalk and leakage noise in dynamic circuits. Recently noise induced chip failures are manifested in static cell based design as well, where the majority of the research has been focused on the noise effect caused by signal delay. However, functional crosstalk noise failures are real even in static CMOS logic devices. For example, a crosstalk noise glitch is injected into a circuit through capacitive coupling, and propagates along the circuit""s path until it either is attenuated by circuit loads, or is amplified and input to a storage element such as a register. If the crosstalk noise glitch is large enough, and reaches the input of the storage element at the right time, a functional failure, or violation, occurs and results in the wrong logic state being stored. Therefore, the design of the static logic devices needs to be analyzed to detect and remove functional failures before the devices are built.
A traditional approach to crosstalk noise analysis is net-centric. This approach simply calculates the glitch noise magnitude at every net in the logic device and reports the nets with glitch magnitudes exceeding a certain DC threshold as potential violators. However, this approach often reports hundreds or even thousands of false violations, which can hide real noise failures and may impose significant and unnecessary costs in the design of the device.
For example, once noise violations are detected, they must be fixed by design changes, such as buffer insertion, driver sizing or rewiring. However, because existing techniques in noise analysis tend to overestimate the number of noise violations, changes are made in the design process to prevent problems that do not really exist. These design changes, in addition to being unnecessary, can be time consuming, because the noise analysis and the resulting design changes take place late in the design process. Hence, reducing the amount of false noise violations is critical to increasing the speed of the design process for new chips.
Because traditional static noise analysis is net-centric, there is a need for a static noise analysis that can detect and report functional failures in a path-centric way.
A method of static noise simulation and analysis includes determining a noise window of a network, determining a sensitive window of the network, and filtering the noise window with the sensitive window.
The noise window of the network may be determined by calculating one or more aggressor noise windows for the network, and combining the aggressor noise windows into a combined noise window. The noise window of the network may be further determined by simulating the propagation of the combined noise window through a logic gate of the network.
The sensitive window of the network may be based on a clock time. For example, the sensitive window may include the clock trigger time, which is when data is clocked-in to data storage elements.
Filtering the noise window with the sensitive window may be performed by calculating an intersection of the noise window and the sensitive window to produce an effective noise window. The method may further include propagating the effective noise window to a register of the network, and determining the noise immunity of the register based on the effective noise window.
Other and further objects, features, aspects, and advantages of the present invention will become better understood with the following detailed description of the accompanying drawings.